1. Field of the Invention
The present invention relates to a silicon wafer which is suitably used as a substrate for an insulated gate bipolar transistor (IGBT) and a method for producing the same. Specifically, the present invention relates to a silicon wafer for IGBT, which is produced through a Czochralski method (CZ method).
Priority is claimed on Japanese Patent Application No. 2005-169929, filed on Jun. 9, 2005, the content of which is incorporated herein by reference.
2. Description of Related Art
An insulated gate bipolar transistor (IGBT) comprises a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided with a PN junction for hole injection. In the IGBT, a gate and an emitter are formed on a surface of an n− type silicon layer having high resistitvity, and a collector is formed on the backside of the n− type silicon layer via a PN junction. An IGBT is an element in which an electric current between the emitter and the collector is controlled by an electric voltage applied to gates intervening a silicon oxide film. In an IGBT, it is possible to reduce the on resistance by injection of hole from the collector to an n− type silicon wafer positioned between the gate, emitter and collector. In addition, an IGBT is not easily destroyed even after a high electric current flows therethrough.
As described above, in the IGBT, an electric current is controlled by the gates intervening an oxide film. Therefore, it is desirable that the gate oxide film be free of defects. In addition, since the current flows between the emitter on the surface of the element and the collector on the back side of the element, defects formed on the wafer have a large influence on the property of the IGBT. Therefore, in the prior art, epitaxial wafers or silicon wafers obtained from a crystal formed by the FZ method (Floating-Zone Melting Method) have been used as a silicon layer for an IGBT.
However, in order to constitute an IGBT of high dielectric resistance, an n− type silicon layer is required to have a thickness of about 100 μm. In order to realize such a thickness by epitaxial growth of the layer, a long production time is required, and therefore an increase in production cost cannot be avoided. When a crystal (FZ crystal) is produced by the FZ method, the amount of impurities contaminating the crystal during a production process of the crystal is smaller than that of a crystal (CZ crystal) produced by a CZ method. Therefore, it is possible to obtain a relatively defect-less silicon wafer by slicing the wafer (FZ wafer) from an FZ crystal, compared to the case in which a silicon wafer (CZ wafer) is sliced from a CZ crystal. On the other hand, it is difficult to produce a large crystal by the FZ method. Therefore, the FZ method is not appropriate for wafers having large diameter, or mass production of wafers.
On the other hand, silicon wafers sliced from a crystal produced by the CZ method include defects comprising microscopic voids of 0.1 to 0.3 μm in size. If such defects are exposed to a surface of a wafer, the defects form pits on the wafer surface. Those defects are generally called as COPs (Crystal Originated Particles). It has been impossible to use a silicon wafer having COPs as it is as a wafer for IGBT. Recently, as described in PCT international publication No. WO 2004/073057 (Patent Document 1), a method for producing a wafer has been developed, in which the numbers of COPs in the wafer have been reduced by performing a heat treatment of a wafer obtained through the CZ method.
Since a large sized crystal can be grown by the CZ method, the CZ method can easily provide a wafer having a large diameter. For example, mass production of wafers having a diameter of 300 mm has been realized. Therefore, a CZ wafer (a wafer sliced from a crystal grown by the CZ method) is suitable as a wafer for large scale integration circuit (LSI). However, CZ wafers have not been used as substrates for IGBT because of the following problems.
Firstly, there is a problem in terms of the yield of GOI (Gate Oxide Integrity). During the growth of a single crystal in the CZ method, excess vacancies occasionally condense to generate void defects of 0.2 to 0.3 μm in size. As described-above, those defects are called COPs. Surface pits formed by the exposure of COPs on the wafer surface or COPs in the vicinity of the wafer surface may be captured in the oxide film layer during a thermal oxidation process causing deterioration of GOI property. Therefore, in order to inhibit the influence on the GOI property, it is necessary to eliminate COPs.
Secondly, there is a problem in terms of fluctuation of resistivity. A silicon single crystal grown by the CZ method (CZ silicon) includes excess oxygen in the order of 1×1018 atoms/cm3. Therefore, by a low temperature heat treatment at a temperature of about 450° C., oxygen donors are caused to occur and fluctuate the resistivity of a substrate. Therefore, it is important to inhibit the occurrence of oxygen donors.
Thirdly, there is a problem in terms of homogeneity in resistivity. Resistivity of a CZ silicon can be controlled by the amount of dopant added to the polycrystalline silicon. However, because of the small segregation coefficient of phosphorus (P), which is an element used in the substrate for an IGBT, concentration of phosphorus varies greatly in the lengthwise direction of a single crystal ingot. Therefore, wafers having a specific resistivity can be obtained only from a narrow portion of a single crystal ingot.
Fourthly, there is a problem in terms of deterioration of the recombination lifetime. As described above, a CZ silicon generally includes oxygen in an order of 1×1018 atoms/cm3. Therefore, during a thermal process accompanied by a device formation process, excess oxygen precipitates to form SiO2 deteriorating the recombination lifetime.
The technology disclosed in Patent Document 1 enables elimination of COPs, which are the factors deteriorating the GOI property. Therefore, the technology is applicable as a method for producing silicon wafers for IGBT. However, the technology described in Patent Document 1 has the following problem. Although the oxygen concentration can be controlled to a level allowing the elimination of COPs, the oxygen concentration may be sufficiently high to cause the above-described generation of oxygen donors, resulting in fluctuation of the resistivity or precipitation of excess oxygen resulting in the deterioration of the recombination lifetime. Especially, the deterioration of the recombination lifetime is highly undesirable in a silicon wafer for IGBT. Therefore, in order to use a silicon wafer as a silicon wafer for an IGBT, it is necessary to reliably inhibit the deterioration of the recombination lifetime, which may be caused by the oxide precipitation, as well as by contamination of heavy metals.
Based on the above-described consideration, an object of the invention is to provide a silicon wafer which is obtained from a silicon ingot grown by the CZ method and is suitably applicable for an IGBT, and a method for producing such a silicon wafer.